This invention relates to the field of integrated circuits, and more specifically to field-effect transistors.
A known field-effect transistor structure 111 is shown in FIG. 1. It includes a first area forming a source 110, a second area forming a drain 120 and rests on a substrate 100 for example based on silicon.
The source 110 and the drain 120 have a substantially rectangular shape and are partially flush with the surface of the substrate 100. The transistor structure 111 also comprises a channel in the form of a block or bar, with a shape similar to that of a parallelepiped, and enabling the source 110 and the drain 120 to be connected in the direction of its length. The channel has a length L measured in a source-drain direction as well as a width W measured in a direction parallel to a main plane of the substrate 100.
The channel is covered by a zone forming a gate 140. The gate 140 is in contact with the channel over a surface S1 (not shown in FIG. 1). The gate makes it possible to control the conduction of the channel and therefore the intensity of a current passing between the source 110 and the drain 120.
It is continuously sought to enhance the performance of transistors by attempting to improve two factors which are normally incompatible: the speed of operation and the consumption of the transistors.
To increase the speed of operation, it is attempted in particular to reduce the size of transistors, which also enables the production costs to be reduced and integrated circuits to be produced with a larger number of transistors.
Reducing the size of transistors involves, for example, bringing the source and the drain closer together and producing a channel with a smaller length and width. This tendency can lead to effects that hinder the good functioning of transistors, such as “short channel effects”. Thus, as the length of the transistor channel is reduced, the drain and the source have an increasing effect on the channel conduction, normally controlled by the gate. “Short channel effects” lead, among other things, to a reduction in the threshold voltage with the channel length and the drain voltage, which leads to an increase in leakage of the transistor while off. This is hardly compatible with the improvement of the performance of integrated circuits.
A second example of a field effect transistor structure 222 is shown in FIG. 2 and presented in the document [1] referenced at the end of this description. This structure makes it possible in part to solve the problem stated above, and in particular to overcome the short channel effects.
The transistor structure 222 is formed on a substrate 100. It includes a first rectangular zone forming a source 210 and a second rectangular zone forming a drain 220 resting on the substrate 100. It also comprises a channel 230 in the form of a plurality of parallelepipedic bars 202 juxtaposed on the substrate 100 and parallel to one another. The bars 202 have lengths L2 and widths W2. They connect, in the direction of their lengths L2 the source 210 and the drain 220.
The bars 202 are mutually separated by spaces 201 having a width We. The channel 230 is covered and in contact over a surface S2 (not shown in FIG. 2) with a gate 240. The extent of the surface S2 influences the value of the threshold voltage of the transistor. It is preferably as small as possible so as to limit the consumption of the transistor, but must be large enough to be capable of ensuring a good current level in the channel 230.
According to document [1], this transistor structure 222 makes it possible to fight against the short channel effects and has better performance in terms of consumption than the conventional transistor structure 111 shown in FIG. 1. Indeed, for equal voltages applied to the gate 140 of the conventional transistor structure 111 and the gate 240 of the second transistor structure 222, with equal contact surfaces S1 and S2 between the gate and the channel, it is possible to obtain a higher channel current for the transistor structure 222 shown in FIG. 2.
The transistor structure 222 nevertheless has problems, in particular in terms of integration density.
This structure, to remain effective, generally takes up more space on a substrate on which it has been formed than a conventional structure such as structure 111 of FIG. 1. To form transistor structure 222 while taking into account constraints in terms of the current, it is attempted to produce bars 202 having the smallest possible widths W2, with spaces 201 between the bars 202 which are also as small as possible. However, the choice of widths W2 of the bars 202, as well as the widths W2 is limited because it is dependent on the minimum sizes that can be obtained by current photolithography and etching methods, or it requires the use of complex photolithographic etching or etching methods that are difficult to reproduce.
In addition to improving the speed and consumption of transistors, it is also continuously sought to improve their integration density on chips or integrated circuits.
A microelectronic device shown in FIG. 3 and described in document [2] referenced at the end of this description in particular proposes a solution for improving the integration density of transistors in a chip. This device includes a substrate 100, preferably electrically insulating, on which three transistors 333a, 333b, 333c, are stacked, having a common gate, and mutually separated by a first inserted first dielectric layer 300a and a second inserted dielectric layer 300b. Each of the transistors 333a, 333b, 333c, comprises a rectangular zone forming a source, respectively designated 310a, 310b, 310c, and a second rectangular zone forming a drain, respectively designated 320a, 320b, 320c. Each of the sources 310a, 310b, 310c and drains 320a, 320b, 320c are respectively connected by parallelepipedic conductive bars forming channels and designated 330a, 330b, 330c. 
In addition, a gate 340 common to the three transistors 333a, 333b, 333c partially covers the stack of channels 330a, 330b, 330c. 